| 主权项 |
1. A computer-implemented method for optimizing a test flow within an ATE (Automated Test Equipment) station for testing at least one semiconductor chip, the test flow listing a plurality of test blocks or tests in a sequence according to which the plurality of test blocks or tests are run, a test block including one or more tests that need to be run together in a specific sequence, the method comprising:
obtaining history data from a storage device, the obtained history data including semiconductor chip test data from previous test operations; determining, based on the obtained history data, a test failure model and one or more of: a test block duration and a yield model, the test failure model determining an order or sequence of the test blocks, the test block duration describing how long it takes for the ATE station to complete all tests in a test block, the yield model describing whether a semiconductor chip is defective or not; scheduling the test flow based on one or more of: the test failure model, the test block duration and the yield model; dynamically reordering the sequence of the tests or the test blocks within the scheduled test flow in real time, the dynamically reordered sequence of the tests or the test blocks minimizing a time to detect a failure in the at least one semiconductor chip; and automatically conducting the tests in the plurality of test blocks on at least one wafer or at least one semiconductor chip according to the scheduled test flow; said determining said test failure model comprises steps of: computing a value Nbf representing a number of semiconductor chips failed within each test block b based on the history data; computing the test block duration tb of each test block b based on the history data; and reordering the plurality of test blocks in a decreasing order of a ratioNbftb. |
