发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make it harder for an element whose bias potential is controlled and which is exposed to severe electric stress and thermal stress to have a failure by delaying a decrease in performance.SOLUTION: A state in which a reference value of stress is exceeded or a state in which a reference value of deterioration is exceeded is detected, and a state of bias control and a state of no bias control are switched in a block of circuits put together for any kind of FET such as a planar type FET, a fin type FET, etc., so as to cancel a state of bias control according to a situation.SELECTED DRAWING: Figure 1
申请公布号 JP2016103803(A) 申请公布日期 2016.06.02
申请号 JP20140242437 申请日期 2014.11.28
申请人 CANON INC 发明人 SASAKI MITSURU
分类号 H03K19/00;H01L21/822;H01L27/04;H03K19/0948 主分类号 H03K19/00
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