SECURE COMPUTING

摘要

Techniques and logic are presented for encrypting and decrypting applications and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual L1 cache memory or between a processor's instruction and execution unit and their respective L1 caches. The logic may include one or more linear feedback shift registers (LFSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used for test purposes.

主权项

1. A multi-processor system comprising two or more processors, each processor including:
an instruction unit configured to process instructions; an execution unit configured to operate on data residing in a cache line within a cache memory containing a plurality of cache lines; at least one interface to a system bus; and logic configured to use a translation code associated with a cache line to translate the data within the cache line;wherein the cache line is read from or written to the cache memory, andwherein the translation codes are not accessible from the system bus.