发明名称 Self-aligned contacts
摘要 A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
申请公布号 US2016155815(A1) 申请公布日期 2016.06.02
申请号 US201514998092 申请日期 2015.12.23
申请人 Intel Corporation 发明人 BOHR Mark T.;GHANI Tahir;RAHHAL-ORABI Nadia M.;JOSHI Subhash M.;STEIGERWALD Joseph M.;KLAUS Jason W.;HWANG Jack;MACKIEWICZ Ryan
分类号 H01L29/51;H01L29/423;H01L29/16;H01L29/78;H01L29/45;H01L29/49 主分类号 H01L29/51
代理机构 代理人
主权项 1. A semiconductor device, comprising: a substrate comprising silicon; a pair of spacers on a portion of the substrate; a gate dielectric layer above a portion of the substrate between the pair of spacers, the gate dielectric layer comprising hafnium and oxygen, wherein the gate dielectric layer is along the portion of the substrate between the pair of spacers and along sidewalls of the pair of spacers; a gate electrode on the gate dielectric layer, wherein a middle portion of the gate electrode has a relatively larger height than side portions of the gate electrode, the side portions of the gate electrode comprising a metal not included in the middle portion of the gate electrode, wherein the side portions comprise titanium and aluminum and not tungsten, and the middle portion comprises tungsten; an insulating cap layer on the top surface of the gate electrode, in contact with a portion of the gate dielectric layer, and between the pair of spacers and substantially coplanar with top surfaces of the pair of spacers, the insulating cap layer having a bottom surface conformal with the middle and side portions of the gate electrode, wherein the insulating cap layer comprises silicon nitride; a diffusion region disposed in the substrate, adjacent to one of the pair of spacers; a metal silicide region on the diffusion region, the metal silicide region having an upper surface having a shape, the metal silicide region comprising titanium; and a contact structure on the metal silicide region, the contact structure disposed in a trench in an interlayer dielectric material laterally adjacent to the pair of spacers, the trench having a bottom opening over a portion of the substrate, the bottom opening over the portion of the substrate having a shape substantially the same as the shape of the upper surface of the metal silicide region.
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