TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE

摘要

An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.

主权项

1. Non-transitory, tangible, computer-readable media containing a program of instructions that, when loaded and run in a computer system, causes the computer system to:
receive a synchronous register transfer logic specification; synthesize a design for a synchronous circuit that contains flip-flops or latches; replace one or more of the flip-flops or latches within the design, each with one or more error-detecting latches; insert one or more asynchronous controllers and one or more delay lines into the design; and output the design after the replace and insert steps.