| 摘要 |
A computer sets a first timing condition for plural registers included in first design information of a semiconductor integrated circuit, and executes first logic synthesis to generate second design information. The computer sets, for the registers, a second timing condition having a smaller timing margin than the first timing condition, and executes second logic synthesis to generate third design information. The computer calculates an area change rate caused by a difference between the timing conditions, on the basis of the second and third design information with respect to each logic cone including a register at its end point, and categorizes the registers into a first group and a second group having smaller change rates than the first group, according to the change rate. The computer executes third logic synthesis with the second timing condition set for the first group and the first timing condition set for the second group. |
| 主权项 |
1. A design method comprising:
generating, by a processor, second design information by setting a first timing condition for a plurality of registers included in first design information of a semiconductor integrated circuit and performing first logic synthesis; generating, by the processor, third design information by setting a second timing condition for the plurality of registers and performing second logic synthesis, wherein the second timing condition has a smaller timing margin than the first timing condition; calculating, by the processor, an area change rate, due to a difference between the timing conditions, of each of a plurality of logic cones each including one of the plurality of registers at an end point, on the basis of the second design information and the third design information; categorizing, by the processor, the plurality of registers into a first group and a second group on the basis of magnitudes of the calculated area change rates, wherein the area change rates of the second group are smaller than the area change rates of the first group; and executing, by the processor, third logic synthesis with the second timing condition being set for first registers of the first group and the first timing condition being set for second registers of the second group. |
