发明名称 RESISTANCE CHANGE MEMORY
摘要 A first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.
申请公布号 US2016155486(A1) 申请公布日期 2016.06.02
申请号 US201615019425 申请日期 2016.02.09
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 IIZUKA Mariko;HATSUDA Kosuke
分类号 G11C11/16 主分类号 G11C11/16
代理机构 代理人
主权项 1. (canceled)
地址 Tokyo JP