发明名称 SEMICONDUCTOR DESIGN METHOD AND COMPUTER-READABLE RECORDING MEDIUM
摘要 A semiconductor design method is disclosed. Bumps are assigned to multiple Input and Output (I/O) sections of a chip. A plane is formed by deploying vias at locations of the bumps which are allocated to I/O sections of power supplies and grounds, with respect to a package on which the chip is mounted. An allocation of the bumps is changed with respect to the I/O sections of the power supplies and the grounds among the multiple I/O sections based on a number of the vias inside a void formed on the plane.
申请公布号 US2016154924(A1) 申请公布日期 2016.06.02
申请号 US201514954253 申请日期 2015.11.30
申请人 Socionext Inc. 发明人 Ozawa Kaname
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A semiconductor design method performed in a computer, the method comprising: assigning, by the computer, bumps to multiple Input and Output (I/O) sections of a chip; arranging, by the computer, a plane by deploying vias at locations of the bumps which are allocated to I/O sections of power supplies and grounds, with respect to a package on which the chip is mounted; and changing, by the computer, an allocation of the bumps with respect to the I/O sections of the power supplies and the grounds among the multiple I/O sections based on a number of the vias inside a void formed on the plane.
地址 Yokohama-shi JP