| 发明名称 |
STATIC TIMING ANALYSIS IN CIRCUIT DESIGN |
| 摘要 |
A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint. |
| 申请公布号 |
US2016154915(A1) |
申请公布日期 |
2016.06.02 |
| 申请号 |
US201514854073 |
申请日期 |
2015.09.15 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Dai Hongwei;Liu Yang;Niu Jia;Ou Peng |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for calculating a path delay in static timing analysis (STA) for a circuit design, the method comprising:
determining a connectivity between a first device and a second device in a path of the circuit design; generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device; and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint. |
| 地址 |
Armonk NY US |
