| 发明名称 |
APPARATUS AND METHOD FOR INCREASING RESILIENCE TO RAW BIT ERROR RATE |
| 摘要 |
Described is an apparatus which comprises: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme, the second encoder to generate a combined codeword having a data portion and a corresponding parity portion, wherein the corresponding parity portion of the combined codeword is to be stored in an additional memory bank of the memory block. |
| 申请公布号 |
US2016156372(A1) |
申请公布日期 |
2016.06.02 |
| 申请号 |
US201414557070 |
申请日期 |
2014.12.01 |
| 申请人 |
INTEL CORPORATION |
发明人 |
MOTWANI RAVI H. |
| 分类号 |
H03M13/29;G06F11/10 |
主分类号 |
H03M13/29 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme, the second encoder to generate a combined codeword having a data portion and a corresponding parity portion. |
| 地址 |
Santa Clara CA US |
