发明名称 LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN
摘要 A method includes the following steps: receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern; with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern; with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern; and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
申请公布号 KR20160061858(A) 申请公布日期 2016.06.01
申请号 KR20150089135 申请日期 2015.06.23
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 CHEN HUANG YU;HOU YUAN TE;KAO YU HSIANG;HSIEH KEN HSIEN;LIU RU GUN;LU LEE CHUNG
分类号 H01L21/027;H01L21/66;H01L21/768;H01L27/02 主分类号 H01L21/027
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