发明名称 SEMI-SHARED SENSE AMPLIFIER AND GLOBAL READ LINE ARCHITECTURE
摘要 A memory includes a global read line and a plurality of banks. For each bank, the memory includes a sense amplifier. A discharge circuit discharges the global read line if any one of a plurality of the sense amplifiers is enabled and is outputting a signal having a first digital logic value onto an input lead of the discharge circuit. In this way, the sense amplifiers share the discharge circuit. In one example, the memory includes a pair of differential read lines that are precharged to begin a read operation. After precharging, if either of two sense amplifiers is enabled and outputting the first digital logic value, then a first discharge circuit discharges a first of the global read lines. If either of two sense amplifiers is enabled and outputting the second digital logic value, then a second discharge circuit discharges a second of the global read lines.
申请公布号 EP2143108(B1) 申请公布日期 2016.06.01
申请号 EP20080732444 申请日期 2008.03.19
申请人 QUALCOMM INCORPORATED 发明人 JUNG, CHANG, HO;CHEN, ZHIQIN
分类号 G11C7/12;G11C7/10;G11C7/18 主分类号 G11C7/12
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