Reduction of edge effects from aspect ratio trapping

摘要

A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.

主权项

1. A method comprising:
forming a first crystalline material in and extending out of an opening, the opening being defined by a dielectric layer on a substrate, the substrate comprising a second crystalline material, the first crystalline material being lattice mismatched to the second crystalline material; forming a third material over and lateral adjoining a lateral edge of the first crystalline material, the third material being more defective than the first crystalline material; planarizing the third material and the first crystalline material to form a planar surface; and forming a device in and/or above the first crystalline material while the third material is more defective than the first crystalline material.