| 摘要 |
A broadband linear amplifier including an input, a first distributed amplifier coupled to the input and having a bias for one of Class A or Class AB operation, the first distributed amplifier including a first plurality of field effect transistors and having a first output, a second distributed amplifier coupled to the input and having a bias for Class C operation, the second distributed amplifier including a second plurality of field effect transistors and having a second output, and a summed output coupled to the first output and the second output, wherein gate widths of the first plurality of field effect transistors monotonically decrease from the input to the first output, and wherein gate widths of the second plurality of field effect transistors monotonically decrease from the input to the second output. |
| 主权项 |
1. A broadband linear amplifier comprising:
an input; a first distributed amplifier coupled to the input and having a bias for one of Class A or Class AB operation, the first distributed amplifier comprising a first plurality of field effect transistors (FETs), each FET of the first plurality of FETs having a gate, a drain and a source, and wherein the first distributed amplifier has a first output; a second distributed amplifier coupled to the input and having a bias for Class C operation, the second distributed amplifier comprising a second plurality of field effect transistors, each FET of the second plurality of FETs having a gate, a drain and a source, and wherein the second distributed amplifier has a second output; a first plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the first plurality of serially connected variable delay lines or transmission line lengths is connected to a respective drain of a respective FET of the first plurality of field effect transistors for tuning the first distributed amplifier, and wherein the first plurality of serially connected variable delay lines or transmission line lengths has a first serial delay line output; a second plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the second plurality of serially connected variable delay lines or transmission line lengths is connected to a respective gate of a respective FET of the first plurality of field effect transistors for tuning the first distributed amplifier, and wherein the second plurality of serially connected variable delay lines or transmission line lengths has a second serial delay line output; a first passive feedback circuit coupled between the second serial delay line output and the first serial delay line output; and a summed output coupled to the first output and the second output; wherein for Class AB operation, the bias for the first distributed amplifier is set above a turn-on threshold voltage for the first distributed amplifier; wherein for Class A operation, the bias for the first distributed amplifier is set higher than for class AB operation and relatively high compared to the turn-on threshold voltage for the first distributed amplifier; and wherein for Class C operation, the bias for the second distributed amplifier is set below a turn-on threshold voltage for the second distributed amplifier; wherein the first passive feedback circuit comprises a resistor connected in series to a capacitor. |
