Circuit test system electric element memory control chip under different test modes

摘要

A circuit test system including a circuit test apparatus and a circuit to be tested is provided. The circuit test apparatus provides a first clock signal. The circuit to be tested includes a plurality of input/output pads and at least one clock pad. At least two input/output pads of the input/output pads are connected to each other to form a test loop during a test mode. The clock pad receives the first clock signal. The circuit to be tested multiplies a frequency of the first clock signal to generate a second clock signal, and the test loop of the circuit to be tested is tested based on the second clock signal during the test mode. The frequency of the second clock signal is higher than that of the first clock signal. Furthermore, a circuit test method of the foregoing circuit test system is also provided.

主权项

1. A circuit test system, comprising:
a circuit test apparatus providing a first clock signal; and a circuit to be tested coupled to the circuit test apparatus, wherein the circuit to be tested comprising:
a plurality of input/output pads, wherein at least two first input/output pads of the input/output pads are connected to each other to form a first test loop during a first test mode;at least one first clock pad receiving the first clock signal; andat least one second clock pad connected to at least one second input/output pad of the input/output pads to form a second test loop during a second test mode, wherein the circuit to be tested multiplies a frequency of the first clock signal to generate a second clock signal, and the first test loop of the circuit to be tested is tested based on the second clock signal during the first test mode, and the first test loop and the second test loop of the circuit to be tested are tested based on the second clock signal during the second test mode, wherein during the second test mode, a read clock is generated based on the second clock signal, outputted from a clock generation unit, and transmitted through a data register unit, a transmission unit of one of the at least two first input/output pads, the at least two first input/output pads, and a reception unit of another one of the at least two first input/output pads in the first test loop, and back to the data register unit, wherein during the second test mode, the read clock is outputted from the clock generation unit, and transmitted through the data register unit, the transmission unit of the at least one second input/output pad, the at least one second input/output pad, the at least one second clock pad, and a reception unit of the at least one second clock pad in the second test loop, and back to the clock generation unit.