Time-to-digital converter, all digital phase locked loop circuit, and method

摘要

The present invention discloses a time-to-digital converter. The time-to-digital converter includes: a phase interpolation circuit and a time-to-digital conversion circuit. The phase interpolation circuit is configured to receive a first reference clock signal and a second reference clock signal; perform phase interpolation on the first reference clock signal and the second reference clock signal to generate a third reference clock signal; and output the third reference clock signal to the time-to-digital conversion circuit. The time-to-digital conversion circuit is configured to receive the third reference clock signal and a fourth clock signal, where a phase difference between the third reference clock signal and the fourth clock signal is less than a phase difference between the first reference clock signal and the fourth clock signal; measure the phase difference between the third reference clock signal and the fourth clock signal; and convert the measured phase difference into a digital signal for outputting.

主权项

1. A time-to-digital converter, comprising: a phase interpolation circuit and a time-to-digital conversion circuit connected to the phase interpolation circuit, wherein
the phase interpolation circuit is configured to receive a first reference clock signal and a second reference clock signal, wherein a phase of the first reference clock signal is prior to a phase of the second reference clock signal; perform phase interpolation on the first reference clock signal and the second reference clock signal to generate a third reference clock signal; and output the third reference clock signal to the time-to-digital conversion circuit; and the time-to-digital conversion circuit is configured to receive the third reference clock signal and a fourth clock signal, wherein a phase difference between the third reference clock signal and the fourth clock signal is less than a phase difference between the first reference clock signal and the fourth clock signal; measure the phase difference between the third reference clock signal and the fourth clock signal; and convert the measured phase difference into a digital signal for outputting, wherein the time-to-digital conversion circuit comprises: a first delay link, a second delay link, and M triggers, wherein M is an integer greater than or equal to 2; a clock input end of a first trigger in the M triggers is configured to input the third reference clock signal, and a data input end of the first trigger is configured to input the fourth clock signal; the first delay link comprises N stages of first delay units connected in series, wherein N=M−1; an input end of a first-stage first delay unit is configured to input the third reference clock signal; and an output end of an xth-stage first delay unit is connected to a clock input end of the (x+1)th trigger in the M triggers, and is configured to input, to the clock input end of an (x+1)th trigger, a third reference clock signal obtained after being delayed by x stages of first delay units, wherein x is an integer greater than zero and less than or equal to N; the second delay link comprises N stages of second delay units connected in series, wherein an input end of a first-stage second delay unit is configured to input the fourth clock signal; and an output end of an xth-stage second delay unit is connected to a data input end of an (x+1)th trigger, and is configured to input, to the clock input end of the (x+1)th trigger, a fourth clock signal obtained after being delayed by x stages of second delay units, wherein a time for which the first delay unit delays is greater than a time for which the second delay unit delays; and output ends of the M triggers are configured to output the digital signal.