Area-efficient clamp for power ring ESD protection using a transmission gate

摘要

Electrostatic discharge (ESD) protection is provided by a charge-latching power-to-ground clamp circuit. A filter capacitor and resistor generate a filter voltage that is buffered by three stages to drive the gate of a BigFET such as a large n-channel transistor. A transmission gate between the stages turns off when BigFET turns on, causing charge to be latched. The filter capacitor can then discharge while the BigFET remains on. A leaker resistor slowly discharges the gate of the large BigFET and turns the transmission gate back on when the BigFET turns off after shunting the ESD current. The length of time that the clamp shunts the ESD current is determined by the leaker resistor and gate capacitance of the BigFET, not by the filter capacitor, so a small filter capacitor may be used.

主权项

1. A core protection circuit for protecting core transistors from electrostatic discharge (ESD) pulses comprising:
a Big Field-Effect Transistor (BigFET), having a drain coupled to a power supply bus, a source coupled to a ground bus, and a gate coupled to a gate node, for shunting current during ESD pulses; an input filter having a filter resistor and a filter capacitor connected in series between the power supply bus and the ground bus, the input filter having a filter node between the filter resistor and the filter capacitor; a plurality of inverters in a chain that includes an initial inverter receiving the filter node as an input and a final inverter outputting the gate node; a transmission gate connected between a sampling output of a sampling inverter in the plurality of inverters and a holding input of a holding inverter in the plurality of inverters, the transmission gate isolating the holding input from the sampling output when the BigFET is turned on, the transmission gate conducting current between the sampling output and the holding input when the BigFET is turned off; wherein the transmission gate comprises:
an n-channel transmission gate transistor having a gate receiving an input to the final inverter;a p-channel transmission gate transistor having a gate receiving the gate node;wherein the p-channel transmission gate transistor and the n-channel transmission gate transistor have conducting channels in parallel between the sampling output and the holding input; a leaker resistor that discharges stored charge to cause the gate node to turn off the BigFET after a predetermined period of time.