发明名称 Vertical type memory device
摘要 A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.
申请公布号 US9356044(B2) 申请公布日期 2016.05.31
申请号 US201514975703 申请日期 2015.12.18
申请人 Samsung Electronics Co., Ltd. 发明人 Seol Kwang-Soo;Cho Seong-Soon
分类号 G11C11/34;G11C16/04;H01L27/115;H01L23/522;H01L23/528 主分类号 G11C11/34
代理机构 Myers Bigel & Sibley, P.A. 代理人 Myers Bigel & Sibley, P.A.
主权项 1. A semiconductor device, comprising: a selection line extending in a first direction; first and second vertically stacked memory cell strings arranged in a second direction crossing the first direction, the first and second vertically stacked memory cell strings commonly coupled to the same selection line; first and second bit lines extending in the second direction, the first bit line spaced apart from the second bit line in the first direction; a first sub-interconnection coupling the first vertically stacked memory cell string to the first bit line; and a second sub-interconnection coupling the second vertically stacked memory cell string to the second bit line, wherein the first sub-interconnection has a first protrusion protruding in the first direction, and wherein the second sub-interconnection has a second protrusion protruding in a direction opposite to the first direction.
地址 KR