Engineered source/drain region for n-Type MOSFET

摘要

Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.

主权项

1. An integrated circuit device, comprising:
a field effect transistor formed on a semiconductor body, the transistor comprising a source region and a drain region which are spaced apart from one another by a channel region in the semiconductor body, and a gate arranged over an upper planar surface of the channel region; wherein the source and drain regions comprise:
a doped silicon carbide (SiC) layer having a planar bottom surface and a recessed upper surface, wherein an outwardly tilted lower sidewall extends upwardly from an outer edge of the planar bottom surface to an outermost tip of the doped SiC layer, and wherein an inwardly tilted upper sidewall extends from the outermost tip of the doped SiC layer to an uppermost point of the recessed upper surface, wherein the uppermost point of the recessed upper surface lies on a plane which is co-planar with the upper planar surface of the channel region;a doped epitaxial silicon layer disposed on the recessed upper surface of the doped SiC layer, the doped epitaxial silicon layer comprising a lower portion disposed below the plane of the upper channel surface and an upper portion that protrudes above the plane of the upper channel surface with an inwardly tilted sidewall, wherein the doped epitaxial silicon layer has a dopant concentration greater than that of the doped SiC layer; anda diffusion extension layer disposed along the bottom surface and lower sidewall of the doped SiC layer and exhibiting a pie-wedge shaped region between the upper sidewall of the doped SiC layer and the plane of the upper channel surface within the semiconductor body.