发明名称 Method of manufacturing a semiconductor device
摘要 A method of manufacturing an RC-IGBT provided with an IGBT and an FWD on the same substrate is provided. First, top surface device structures of an IGBT and an FWD are formed on the top surface of a semiconductor substrate. Then, with the side of an IGBT region on the top surface of the semiconductor substrate shielded by a first shielding mask, only an FWD region is irradiated with light ions. Next, with the side of the FWD region on the bottom surface of the semiconductor substrate shielded by a second shielding mask, only the IGBT region is irradiated with light ions. With this, a first lifetime control region 10-1 is formed on the collector side A2 in the IGBT region A1-A2 and a second lifetime control region 10-2 is formed on the anode side B1 of the FWD region B1-B2.
申请公布号 US9356115(B2) 申请公布日期 2016.05.31
申请号 US201313845066 申请日期 2013.03.17
申请人 FUJI ELECTRIC CO., LTD. 发明人 Mizushima Tomonori
分类号 H01L29/66;H01L29/739;H01L29/861 主分类号 H01L29/66
代理机构 Rabin & Berdo, P.C. 代理人 Rabin & Berdo, P.C.
主权项 1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate having a first semiconductor element provided in a first region on one side of the semiconductor substrate, and a second semiconductor element provided in a second region on another side of the semiconductor substrate to be side-by-side with the first semiconductor element, the semiconductor substrate being a semiconductor substrate of a first conduction type that is provided with an insulated gate structure as a top surface element structure of the first semiconductor element, the insulated gate structure including a base region of a second conduction type, an emitter region of the first conduction type and a gate electrode, that is provided with an anode region of the second conduction type as a top surface element structure of the second semiconductor element, that is provided with a collector region of the second conduction type as a bottom surface element structure of the first semiconductor element, and that is provided with a cathode region of the first conduction type as a bottom surface element structure of the second semiconductor element; preparing a light ion source and a mask; shielding the first region by providing a mask on a top surface of the semiconductor substrate on said one side of the semiconductor substrate; irradiating the top surface of the semiconductor substrate with light ions by operating a light ion source to introduce lattice defects at a specified depth within the second region through the top surface of the semiconductor substrate; and irradiating a bottom surface of the semiconductor substrate with light ions by operating the light ion source to introduce lattice defects at a specified depth on the entire bottom surface within the semiconductor substrate; wherein the first semiconductor element has a minimum carrier lifetime value that is longer than that of the second semiconductor element; wherein the anode region of the second semiconductor element has a carrier lifetime that is made shorter during irradiating the top surface of the semiconductor substrate (a) than that of the emitter region of the first semiconductor element which is protected by the mask during irradiating, and (b) than that of the cathode region of the second semiconductor element; wherein the collector region has a carrier lifetime that is made shorter during irradiating the entire bottom surface of the semiconductor substrate than that of the cathode region, and wherein the first semiconductor element includes an IGBT region, the second semiconductor element includes an FWD region, and the semiconductor substrate has a drift region in which is defined a depth region formed at a predetermined depth, D, that includes at least a portion of the IGBT region and at least a portion of the FWD region, the depth region having a carrier lifetime that is shortened in both the IGBT region and the FWD region to provide respective short carrier lifetime regions, provided that the short carrier lifetime region of the IGBT region has a rear surface having a depth that is greater than that of the short carrier lifetime region of the FWD region.
地址 Kawasaki-Shi JP