发明名称 |
Semiconductor arrangement |
摘要 |
A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided. |
申请公布号 |
US9356020(B2) |
申请公布日期 |
2016.05.31 |
申请号 |
US201414289766 |
申请日期 |
2014.05.29 |
申请人 |
Taiwan Semiconductor Manufacturing Company Limited |
发明人 |
Colinge Jean-Pierre;Dhong Sang Hoo;Guo Ta-Pen;Wu Chung-Cheng |
分类号 |
H01L29/10;H01L21/02;H01L27/088;H01L29/06;H01L29/78;H01L29/66;B82Y10/00;B82Y40/00;H01L29/423;H01L29/775;H01L21/8234 |
主分类号 |
H01L29/10 |
代理机构 |
Cooper Legal Group, LLC |
代理人 |
Cooper Legal Group, LLC |
主权项 |
1. A semiconductor arrangement comprising:
a first semiconductor device comprising:
a first type region having a first conductivity type, a second type region having a second conductivity type, and a first channel region between the first type region and the second type region; a second semiconductor device adjacent the first semiconductor device, the second semiconductor device comprising:
a third type region having a third conductivity type, a fourth type region having a fourth conductivity type, and a second channel region between the first type region and the second type region; a first insulator layer comprising a first insulator portion having a first sidewall in contact with the first semiconductor device and a second insulator portion having a second sidewall in contact with the second semiconductor device, the first sidewall having a first insulator height and the second sidewall having a second insulator height, wherein the first insulator height is different than the second insulator height; and a dielectric layer over a top surface of the first insulator layer, the dielectric layer having a first sidewall in contact with the first channel region and a second sidewall in contact with the second channel region. |
地址 |
Hsin-Chu TW |