Receiver circuit for receiving an input signal

摘要

A receiver circuit for receiving an input signal (IDD, UDD) comprises a detector circuit (111, 111a, 111b, 111c, 111d, 111e, 111f), which is in the form of a sample-and-hold circuit for determining a reference level of the input signal or in the form of a filter circuit for generating a mean value of levels of the input signal (IDD, UDD). The detector circuit generates, on the output side, a referential signal (RS), which is supplied to comparator circuits (113a, 113b, 113c, 113d, 115a, 115b, 115c, 115d). The comparator circuits (113a, 113b, 113c, 113d, 115a, 115b, 115c, 115d) compare an offset level of the input signal (IDD, UDD) with the referential signal (RS) and generate data signals (DATA, DH, DL). The offset input signals (IDD, UDD) are evaluated relatively in respect of the reference level or the mean value of the levels of the input signal.

主权项

1. A receiver circuit for receiving an input signal, comprising:
an input connection for applying the input signal; a detector circuit for generating a referential signal, wherein the detector circuit is designed to detect a level of the input signal and to generate a reference level of the referential signal depending on the detected level of the input signal, wherein the detector circuit comprises a controllable switch being controlled to be switched to an on-state during an initialization phase to connect the input connection to the detector circuit and to store the reference level of the referential signal in the detector circuit and to be switched in an off-state after the initialization phase, and wherein the reference level of the referential signal continues to be stored in the detector circuit after the initialization phase; an offset circuit for generating a comparison signal, wherein the offset circuit is connected to the input connection, and wherein the offset circuit is designed to add an offset level to the level of the input signal and to generate a level of the comparison signal depending on the addition; and a comparator circuit for generating a level of a data signal, wherein the comparator circuit is connected to the offset circuit and the detector circuit, and wherein the comparator circuit is designed to generate the level of the data signal depending on a comparison of the reference level of the referential signal with the level of the comparison signal.