Method for asynchronous gating of signals between clock domains

摘要

An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit. The circuitry may de-assert a first enable signal dependent upon a first clock signal. The synchronization circuit may generate a second enable signal synchronized to a second clock signal and may de-assert the second enable signal in response to de-asserting the first enable signal. The clock gate circuit may generate a third clock signal dependent upon the second clock signal, and may disable the third clock signal responsive to de-asserting the second enable signal. The circuitry may further disable the second clock signal in response to determining a predetermined period of time has elapsed since de-asserting the first enable signal.

主权项

1. An apparatus, comprising:
circuitry configured to:
generate a first enable signal dependent upon a first clock signal;generate a second clock signal in response to an assertion of the first enable signal, wherein a frequency of the second clock signal is greater than a frequency of the first clock signal; anddetermine that a first predetermined period has elapsed since a de-assertion of the first enable signal; a synchronization circuit configured to:
generate a second enable signal synchronized to the second clock signal; andde-assert the second enable signal in response to a determination that the first enable signal has been de-asserted; and a clock gate circuit configured to:
generate a third clock signal dependent upon the second clock signal; anddisable the third clock signal in response to the de-assertion of the second enable signal; wherein the circuitry is further configured to disable the second clock signal in response to a determination that the first predetermined period of time has elapsed; wherein the circuitry includes a delay circuit, and wherein to determine that the first predetermined period of time has elapsed, the circuitry is further configured to delay the first enable signal using the delay circuit.