发明名称 Semiconductor device
摘要 A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL0) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL1) that is another part thereof according to a second write command with respect to the physical address.
申请公布号 US9355719(B2) 申请公布日期 2016.05.31
申请号 US201214415706 申请日期 2012.07.19
申请人 Hitachi, Ltd. 发明人 Miura Seiji;Uchigaito Hiroshi;Kurotsuchi Kenzo
分类号 G11C8/00;G11C13/00;G06F12/02;G11C29/24;G11C29/04;G11C16/04 主分类号 G11C8/00
代理机构 Miles & Stockbridge P.C. 代理人 Miles & Stockbridge P.C.
主权项 1. A semiconductor device comprising: a nonvolatile memory unit that includes a plurality of memory cells; and a control circuit that allocates a physical address to a logical address input from outside to perform access to the physical address of the nonvolatile memory unit, wherein the nonvolatile memory unit includes a plurality of first signal lines, a plurality of second signal lines that intersect the plurality of first signal lines, and a plurality of memory cell groups disposed at intersections of the plurality of first signal lines and the plurality of the second signal lines, each of the plurality of memory cell groups includes first to N-th (N is an integer of 2 or greater) memory cells, and first to N-th memory cell selection lines that respectively select the first to N-th memory cells, and the control circuit writes data to a first portion that includes M (M<N) memory cells among the first to N-th memory cells according to a first write command to a first physical address, and writes data to a second portion that includes M memory cells excluding the first portion among the first to N-th memory cells according to a second write command to the first physical address generated after the first write command.
地址 Tokyo JP