Control circuit with hysteresis for a switching voltage regulator and related control method

摘要

A control circuit for a switching voltage regulator is configured to receive an error signal representative of a regulator output voltage in relation to a nominal output voltage, and includes a set/reset flip-flop, a hysteresis comparator and a logic circuit. The flip-flop is configured to produce a switching control signal according to logic values at its set and reset terminals. The comparator is configured to produce a set signal at the set terminal when an error signal drops below a first value, and a reset signal when the error signal rises above a second value. The logic circuit is configured to prevent transmission of the reset signal to the reset terminal during a selected minimum time period and to thereafter enable transmission of the reset signal, and further, to produce an alternate reset signal at the reset terminal at the end of the selected maximum time period.

主权项

1. A control circuit, comprising:
a hysteresis comparator configured to receive an error voltage and to generate first and second logic signals that become logically active respectively when the error voltage is below a lower threshold and above a higher threshold; a set/reset flip-flop configured to generate a regulator control signal according to the logic values assumed by said first and second logic signals; a first monostable multivibrator configured to output a first logic value for a minimum time interval starting from an active edge of said first logic signal, and to otherwise output a second logic value; a second monostable multivibrator configured to output a third logic value for a maximum time interval starting from the active edge of said first logic signal and to otherwise output a fourth logic value; and logic gates configured to reset said set/reset flip-flop when said second logic signal is active and said first monostable multivibrator outputs the second logic value to prevent reset of said set/reset flip-flop by said second logic signal before the minimum time interval has elapsed from the active edge of said first logic signal, the logic gates are configured to reset said set/reset flip-flop when said second monostable multivibrator outputs the fourth logic value to ensure reset of said set/reset flip-flop by the end of the maximum time interval from the active edge of the first logic signal.