Programmable logic device

摘要

A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.

主权项

1. A semiconductor device comprising:
a first circuit; a second circuit; and an output portion, wherein the first circuit comprises:
a first transistor;a first capacitor; anda first inverter, wherein one of a source and a drain of the first transistor is electrically connected to the first capacitor and an input portion of the first inverter, wherein the second circuit comprises a second transistor, wherein an output portion of the first inverter is electrically connected to one of a source and a drain of the second transistor, and wherein the other of the source and the drain of the second transistor is electrically connected to the output portion.