| 发明名称 | Method and apparatus for instruction scheduling using software pipelining | ||
| 摘要 | A method for scheduling loop processing of a reconfigurable processor includes generating a dependence graph of instructions for the loop processing; mapping a first register file of the reconfigurable processor on an arrow indicating inter-iteration dependence on the dependence graph; and searching for schedules of the instructions based on the mapping result. | ||
| 申请公布号 | US9354850(B2) | 申请公布日期 | 2016.05.31 |
| 申请号 | US201414507272 | 申请日期 | 2014.10.06 |
| 申请人 | SAMSUNG ELECTRONICS CO., LTD. | 发明人 | Ahn Min-wook;Kim Won-sub;Jin Tai-song;Lee Seung-won;Lee Jin-seok |
| 分类号 | G06F9/45 | 主分类号 | G06F9/45 |
| 代理机构 | Staas & Halsey LLP | 代理人 | Staas & Halsey LLP |
| 主权项 | 1. A method for scheduling processing of a loop in a reconfigurable processor, the method comprising: generating a dependence graph of instructions for the processing of the loop; detecting an arrow of the dependence graph indicating inter-iteration dependence on the dependence graph; mapping a register file of the reconfigurable processor on the detected arrow of the dependence graph indicating the inter-iteration dependence on the dependence graph; and searching for schedules of the instructions for the processing of the loop based on the mapping. | ||
| 地址 | Suwon-Si KR | ||