METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE

摘要

An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

主权项

1. An apparatus, comprising:
a plurality of cores, wherein a first core of the plurality of cores is configured to process a plurality of instructions; and circuitry coupled to the first core, wherein the circuitry is configured to:
detect that the first core has stopped committing a subset of the plurality of instructions; andsend an indication to a second core of the plurality of cores that the first core has stopped committing the subset of the plurality of instructions; wherein the second core is configured to:
disable the first core from further processing instructions of the subset of the plurality of instructions responsive to receiving the indication; andcopy data from at least one memory location in the first core to at least one memory location in a third core of the plurality of cores responsive to disabling the first core; and wherein the third core is configured to resume processing the subset of the plurality of instructions dependent upon the data.