发明名称 3-PORT BITCELL ARRAY WITH SHARED FIRST AND SECOND GLOBAL READ WORD LINES AND GLOBAL WRITE WORD LINE ON SAME METAL LAYER
摘要 An apparatus includes an array of bit cells (202, 204, 206, 208) that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line (240) configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line (244) configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line (242) configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer (M4).
申请公布号 WO2016081158(A1) 申请公布日期 2016.05.26
申请号 WO2015US57362 申请日期 2015.10.26
申请人 QUALCOMM INCORPORATED 发明人 MOJUMDER, NILADRI NARAYAN;SONG, STANLEY SEUNGCHUL;WANG, ZHONGZE;LIU, PING;RIM, KERN;YEAP, CHOH FEI
分类号 G11C8/14;G11C8/16;H01L27/06 主分类号 G11C8/14
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