| 发明名称 |
PAUSIBLE BISYNCHRONOUS FIFO |
| 摘要 |
A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted. |
| 申请公布号 |
US2016148661(A1) |
申请公布日期 |
2016.05.26 |
| 申请号 |
US201514948175 |
申请日期 |
2015.11.20 |
| 申请人 |
NVIDIA Corporation |
发明人 |
Keller Benjamin Andrew;Fojtik Matthew Rudolph;Khailany Brucek Kurdo |
| 分类号 |
G11C7/22;G11C7/10 |
主分类号 |
G11C7/22 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method, comprising:
writing data synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array; generating an increment signal in the first clock domain; determining that the increment signal transitions near an edge of a second clock signal, wherein the second clock signal is a pausible clock signal; delaying a next edge of the second clock signal of the second clock domain; and transmitting the increment signal to the second clock domain. |
| 地址 |
Santa Clara CA US |
