DATA PROCESSING APPARATUS HAVING COMBINED DIVIDE-SQUARE ROOT CIRCUITRY

摘要

A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.

主权项

1. A data processing apparatus comprising:
combined divide-square root circuitry to perform, in response to a divide instruction identifying a first operand A and a divisor D, a radix-N SRT division algorithm to generate a result value Q=A/D, and to perform, in response to a square root instruction identifying a second operand B, a radix-N SRT square root algorithm to obtain a result value Q=√{square root over (B)}, where N is an integer power of 2; wherein the SRT division algorithm and the SRT square root algorithm each comprise a plurality of iterations, each iteration for determining an updated remainder value Ri based on a quotient value qi selected for that iteration in dependence on a previous remainder value Ri−1, the updated remainder value from one iteration becoming the previous remainder value for a following iteration, and the result value Q being derivable from the quotient values selected for the plurality of iterations; and the combined divide-square root circuitry comprises shared remainder updating circuitry to generate the updated remainder value for a greater number of iterations per processing cycle for the SRT division algorithm than for the SRT square root algorithm.