发明名称 MULTILAYER WIRING BOARD MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a multilayer wiring board manufacturing method which allows a wiring width of the multilayer wiring board to be formed at a narrow pitch and allows solder bumps on the multilayer wiring board to be formed at a narrow pitch.SOLUTION: A multilayer wiring board manufacturing method comprises: a seed layer formation process of forming seed layers on a surface and a rear face of an insulating substrate in an interlayer connection state; a wiring plating resist formation process of forming a wiring plating resist on a surface of each seed layer; an electrolytic copper plating process of performing electrolyte copper plating to form a wiring layer on each seed layer; an electrode plating resist formation process of forming an electrode plating resist on the wiring layer and the wiring plating resist except an electrode formation scheduled part; a solder plating process of forming a solder plating layer on the electrode formation scheduled part; a plating resist removal process of removing the wiring plating resist and the electrode plating resist; an etching process of removing the seed layer exposed after the plating resist removal process; and a solder resist formation process of forming a solder resist layer with a formation portion of the solder plating layer being left.SELECTED DRAWING: Figure 2
申请公布号 JP2016096245(A) 申请公布日期 2016.05.26
申请号 JP20140231518 申请日期 2014.11.14
申请人 MITSUBISHI MATERIALS CORP 发明人 NAKAYA KIYOTAKA;MAWATARI FUYUMI;WATANABE MASAMI
分类号 H05K3/24;H05K3/18 主分类号 H05K3/24
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