CAPACITANCE REDUCTION FOR ADVANCED TECHNOLOGY NODES

摘要

After forming source/drain contact trenches to expose source/drain regions, contact liner material layer portions are formed on sidewalls and bottom surfaces of the source/drain contact trenches. Contact material layer portions are then formed over the contact liner material layer portions to fill in the source/drain contact trenches. At least portions of the contact material layer portions and the contact liner material layer portions present on sidewalls of the source/drain contact trenches are removed to provide source/drain contacts with reduced contact capacitance.

主权项

1. A method of forming a semiconductor structure comprising:
forming source/drain regions on opposite sides of at least one gate structure located on a channel region of a semiconductor material layer; forming source/drain contact trenches through a contact level dielectric layer and at least a portion of an interlevel dielectric (ILD) layer underlying the contact level dielectric layer, each of the source/drain contact trenches exposing at least a portion of one of the source/drain regions; forming contact liner material layer portions on sidewalls and bottom surfaces of the source/drain contact trenches; forming contact material layer portions to fill remaining volumes of the source/drain contact trenches; forming a patterned mask layer to cover portions of contact liner material layer portions and contact martial layer portions in the source/drain contact trenches; removing at least portions of exposed portions of the contact liner material layer portions present on the sidewalls of the source/drain trenches and exposed portions of the contact material layer portions to provide voids; and forming dielectric layer portions to fill the voids.