发明名称 REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS
摘要 An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.
申请公布号 US2016148993(A1) 申请公布日期 2016.05.26
申请号 US201414550350 申请日期 2014.11.21
申请人 International Business Machines Corporation 发明人 Basu Anirban;Majumdar Amlan;Sleight Jeffrey W.
分类号 H01L29/06;H01L29/66;H01L29/78 主分类号 H01L29/06
代理机构 代理人
主权项 1. A method of forming a baffler in a vertical field effect transistor with low effective mass channel materials, comprising: forming a first source/drain contact on a semiconductor substrate; forming a channel with a first channel layer on the first source/drain contact, a barrier on the first channel layer, and a second channel layer on the baffler; and forming a second source/drain contact on the second channel layer.
地址 Armonk NY US