SYMBOL TRANSITION CLOCKING CLOCK AND DATA RECOVERY TO SUPPRESS EXCESS CLOCK CAUSED BY SYMBOL GLITCH DURING STABLE SYMBOL PERIOD

摘要

A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a first set-reset latch that provides a filtered version of the comparison signal, where the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time, delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal, and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal.

主权项

1. A clock recovery circuit, comprising:
a comparator configured to provide a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, wherein the input signal represents signaling state on a plurality of signal wires; a first set-reset latch that provides a filtered version of the comparison signal, wherein the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time; delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal; and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal, wherein the second set-reset latch is reset when no pulse is present on the first clock signal.