COMPACT SAMPLE-AND-HOLD DEVICE

摘要

The sample-and-hold device comprises a holding capacitor and operates according to a track phase during which the voltage on the terminals of the capacitor tracks the input signal and according to a hold phase during which the capacitor is isolated from the input signal, it comprises: a differential pair comprising a first transistor Q1 and a second transistor Q2 connected as common emitters, the collector of the transistor Q2 being connected to the holding capacitor, the input signal being applied to the base of the transistor Q1; a third transistor Q3, of which the base is connected to the collector of the transistor Q2 and the emitter is connected to the base of the transistor Q2, the signal present on the emitter of the transistor Q3 forming the output signal of the sample-and-hold device; a current source I connected to the collector of the transistor Q2; during the track phase, the differential pair Q1, Q2 being supplied by a current 2I, the transistor Q2 being charged by the current source and by the holding capacitor, during the hold phase, the current 2I supplying the differential pair Q1, Q2 being disconnected and the holding capacitor being charged by two opposite currents having the same value, equal to the current I of the source.

主权项

1. A sample-and-hold device comprising a holding capacitor, said sample-and-hold device operating according to a track phase during which the voltage on the terminals of said capacitor tracks the input signal of said sample-and-hold device and according to a hold phase during which the capacitor is isolated from said input signal, said sample-and-hold device comprising at least:
a differential pair comprising a first bipolar transistor Q1 and a second bipolar transistor Q2 connected as common emitters, the collector of the transistor Q2 being connected to the holding capacitor, the input signal being applied to the base of the transistor Q1; a third bipolar transistor Q3, of which the base is connected to the collector of the transistor Q2 and the emitter is connected to the base of the transistor Q2, the signal present on the emitter of the transistor Q3 forming the output signal of said sample-and-hold device; a current source connected to the collector of the transistor Q2; during the track phase, said differential pair Q1, Q2 being supplied by a current 21, the transistor Q2 being charged by said current source and by the holding capacitor, during the hold phase, the current 2I supplying the differential pair Q1, Q2 being disconnected and the holding capacitor being charged by two opposite currents having the same value, equal to the current of said source.