发明名称 Multi-element comparison and multi-element addition
摘要 Disclosed is an apparatus 8 to selectively perform multi-element comparison and addition on packed data items such as vectors. The apparatus has non-final reduction stages, each with a non-final intermediate operand forming stage 10 to form intermediate operands from an input vector and intermediate sum values output from a preceding non-final reduction stage. The non-final stages also have carry propagate adders stages 12 to add respective pairs of the intermediate operands to form intermediate sum values. A final reduction stage has a final intermediate operand stage 16 that forms final intermediate operands from intermediate sum values output from the non-final reduction stages. The final stage also has an output adder stage 18 to generate an output by adding the final intermediate operands. The reduction stages may also have a non-final limit value selecting stage 14 active when performing a multi-element comparison, to select in dependence upon the carry values generated by the carry propagate adders stage, limit values that are the larger or smaller value of a pair of elements.
申请公布号 GB2532562(A) 申请公布日期 2016.05.25
申请号 GB20150016457 申请日期 2015.09.17
申请人 ARM Limited 发明人 David Raymond Lutz;Neil Burgess
分类号 G06F15/80;G06F9/302;G06F17/16 主分类号 G06F15/80
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