发明名称 埋込み層に低抵抗コンタクトを形成する打込み領域を含んだ半導体デバイスの製作方法および関連したデバイス
摘要 Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.
申请公布号 JP5926216(B2) 申请公布日期 2016.05.25
申请号 JP20130099518 申请日期 2013.05.09
申请人 クリー インコーポレイテッドCREE INC. 发明人 スコット ティー.シェパード;アレクサンダー ブイ.スボーロフ
分类号 H01L21/338;H01L21/265;H01L21/28;H01L21/318;H01L29/417;H01L29/423;H01L29/778;H01L29/812 主分类号 H01L21/338
代理机构 代理人
主权项
地址
您可能感兴趣的专利