| 摘要 |
FIELD: information technology.SUBSTANCE: hybrid flow microprocessor comprises a system controller, connected by buses to second-level cache and to a memory control unit, which is in turn connected by buses to an instruction buffer for querying instructions, an integer ALU and a floating point arithmetic unit, which is connected by a bus to the second-level cache, the instruction buffer is connected by buses to the integer ALU, the floating point arithmetic unit and by an additional bus to the memory control unit for issuing instructions thereto, wherein the microprocessor is further provided with an instruction redecoding unit for converting instructions into the microprocessor internal code and redecoding instructions for a flow computer with input and output buses, the flow computer and a flow computer control unit for synchronising operation of the flow computer with a microprocessor pipeline and data communication with cache, wherein the said instruction redecoding unit is connected by an input bus to the second-level cache to receive instructions and by an output bus to the memory control unit to transmit the converted instructions in the microprocessor internal code and the redecoded instructions for the flow computer, wherein the said flow computer control unit is connected by buses to the instruction buffer to receive instructions, to the memory control unit and to the second-level cache for data communication, and to the flow computer for control thereof and data communication.EFFECT: broader technological capabilities by translating RISC architecture instructions into control commands of a flow computer, and high efficiency of the microprocessor due to the independent execution of commands in the flow computer without blocking the main microprocessor pipeline.2 dwg |
