| 摘要 |
A repair circuit of the present invention includes: a column repair signal generation block for comparing an input address with respective first and second repair addresses in response to a mode control signal, and generating first and second column repair signals; a normal decoder for accessing one of a first normal column line corresponding to the input address and a second normal column line which is only different from a most significant bit of the input address in response to the first and second column repair signals; and a redundancy decoder for decoding the first repair address in response to the first and second column repair signals. The first and second repair addresses are provided with a repair circuit where only a most significant bit is different, and a test on the second normal column line is performed in the case that the first column line is repaired from the first and the second column lines where only a most significant bit is different in a test mode of a double column line. In addition, time spent during the test is reduced by accessing the double column line to perform the test even after the repair operation. |
