ALGORITHM TO ACHIEVE OPTIMAL LAYOUT OF INSTRUCTION TABLES FOR PROGRAMMABLE NETWORK DEVICES

摘要

A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

主权项

1. A processing network comprising:
a plurality of processing elements on a programmable microchip, wherein each of the processing elements have one or more instruction tables each including one or more blocks; a plurality of on-chip routers on the microchip for routing the data between the processing elements, wherein each of the on-chip routers is communicatively coupled with one or more of the processing elements; and a compiler stored on a non-transitory computer-readable memory and comprising an instruction table mapper that maps one or more instructions derived from assignments of a source code into one or more lines of the blocks of the instruction tables.