INTEGRATED CIRCUIT PERFORMANCE MODELING USING A CONNECTIVITY-BASED CONDENSED RESISTANCE MODEL FOR A CONDUCTIVE STRUCTURE IN AN INTEGRATED CIRCUIT

摘要

Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.

主权项

1. An integrated circuit performance modeling system comprising:
a memory storing a design layout of an integrated circuit; an integrated circuit design layout analyzer in communication with said memory, said integrated circuit design layout analyzer accessing said memory and analyzing said design layout in order to identify, within said design layout, a diffusion boundary shape of a semiconductor device, a first conductive shape on said diffusion boundary shape, any second conductive shapes connected to said first conductive shape and, for each second conductive shape identified as being connected to said first conductive shape, a corresponding interface location between said second conductive shape and said first conductive shape relative to said diffusion boundary shape; a model library storing a plurality of connectivity-based condensed resistance models for conductive shapes; a model selector in communication with said integrated circuit design layout analyzer and said model library, said model selector accessing said model library and selecting, from said model library, a specific condensed resistance model for said first conductive shape based on any corresponding interface locations between said first conductive shape and any second conductive shapes relative to said diffusion boundary shape; a netlist extractor in communication with said model selector and generating a condensed netlist for said first conductive shape based on said specific condensed resistance model; and a simulator in communication with said netlist extractor and simulating a performance of said integrated circuit using said condensed netlist for said first conductive shape.