发明名称 ERROR CORRECTION APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide an error correction apparatus configured to properly control write operation and read operation, while minimizing the time required for the write operation and read operation.SOLUTION: A degradation determination circuit 21 determines an erasure time ratio information DR with respect to a reference erasure time BDT of a measured erasure time TD after erasure operation, and obtains a block unit/cell deterioration determination value JC (B), on the basis of the erasure time ratio information DR and block unit/write time information JW (B), according to a determination condition using the erasure time ratio information DR, upper write time ratio information JW1, and lower write time ratio information JW2, as criteria. The block unit/cell deterioration determination value JC(B) is stored in a block unit determination result storage section 36. A general control section 11 controls read operation and write operation with an error correction capability using the block unit/cell deterioration determination value JC(B) as a criterion.SELECTED DRAWING: Figure 9
申请公布号 JP2016085671(A) 申请公布日期 2016.05.19
申请号 JP20140219231 申请日期 2014.10.28
申请人 MEGA CHIPS CORP 发明人 TAMURA MITSURU
分类号 G06F12/16 主分类号 G06F12/16
代理机构 代理人
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