POWER SYSTEM SUB-SYNCHRONOUS OSCILLATION DAMPER

摘要

A control circuit for power system sub-synchronous oscillation dampening is described. The control circuit is configured to provide low impedance at sub-synchronous frequencies and high impedance at the fundamental frequency. The control circuit includes an input configured to receive a direct voltage value and a quadrature voltage value. Both the direct voltage value and the quadrature voltage value are based on a three-phase voltage. At least one controller configured to determine a direct current value and a quadrature current value based at least in part on the direct voltage value and the quadrature voltage value is included. The control circuit also includes an output configured to send the direct current value and the quadrature current value as feed forward signals to a control loop for the three-phase voltage.

主权项

1. A control circuit comprising:
an input configured to receive a direct voltage value and a quadrature voltage value, wherein both the direct voltage value and the quadrature voltage value are based on a three-phase voltage; at least one controller configured to determine a direct current value and a quadrature current value based at least in part on the direct voltage value, the quadrature voltage value and a voltage phase angle derived from a phase lock loop (PLL); and an output configured to send the direct current value and the quadrature current value as feed forward signals to a control loop for the three-phase current, wherein the control circuit is configured to provide low impedance at sub-synchronous frequencies and high impedance at a fundamental frequency.