| 摘要 |
An apparatus for controlling memory includes a memory controller, and a data interface that interfaces with and is in data communication with data lines, each having inherent skew. Each data line carries a data signal. The data lines connect the memory controller to the memory. The apparatus also includes data de-skewers, each associated with a corresponding data line, a strobe interface that interfaces with a strobe line that connects the memory controller to the memory and that applies a timing signal to the strobe line, and a strobe de-skewer connected to the strobe line. Each data de-skewer operates in read or write mode. A particular data line's data de-skewer applies a compensation skew to a data signal carried by that line. |
| 主权项 |
1. An apparatus for controlling a memory, said apparatus comprising: a memory controller, a data interface that interfaces with data lines that connect said memory controller to said memory, a plurality of data de-skewers, each of said data de-skewers being associated with a corresponding one of said data lines, a strobe interface that interfaces with a strobe line that connects said memory controller to said memory, and a strobe de-skewer that is in communication with said strobe line, wherein each of said data lines carries a data signal, wherein said data interface is in data communication with each of said data lines, wherein said strobe interface is configured to apply a timing signal to said strobe line, wherein each of said data de-skewers is configured to operate in a write mode, in which a bit is to be written to said memory, and in a read mode, in which a bit is to be read from said memory, wherein said data de-skewer that corresponds to said data line is configured to apply a compensation skew to a data signal that is carried by said data line, wherein when said data de-skewer is being operated in said write mode, said data signal represents a bit that is to be written to said memory, and wherein when said data de-skewer is being operated in said read mode, said data signal represents a bit that has been read from said memory, wherein each of said data lines has an inherent skew, wherein each of said data de-skewers applies a compensation-skew to a data signal that is being carried by a data line with which said data de-skewer corresponds, and wherein said strobe de-skewer is configured to skew said timing signal by an amount that is selected to be one of less than and equal to a maximum delay of said strobe de-skewer and one of greater than and equal to a minimum delay of said strobe de-skewer. |
