METHOD TO MEASURE EDGE-RATE TIMING PENALTY OF DIGITAL INTEGRATED CIRCUITS

摘要

Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit.

主权项

1. A method for improving the accuracy of a static-timing circuit model that is used to model digital integrated circuits, the method comprising:
evaluating a first timing delay of a first circuit element in a ring oscillator circuit using a statistical model, wherein the first circuit element is arranged in the ring oscillator to have a large edge-rate at its input and a small edge-rate at its output; evaluating a second timing delay of the first circuit element using a fixed-corner model; calculating a timing delay error between the first timing delay and the second timing delay; and correcting a computed timing delay determined by the static-timing circuit model for a second circuit element in an analyzed digital integrated circuit by an amount based on the determined timing delay error.