Embedded JFETs for High Voltage Applications

摘要

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

主权项

1. A device comprising:
a buried well region of a first conductivity type over a substrate layer; a first High Voltage Well (HVW) region of the first conductivity type over the buried well region; an insulation region over the first HVW region; a drain region of the first conductivity type on a first side of the insulation region; a gate electrode on a second side of the insulation region; a well region in a region adjacent to the insulation region, wherein the well region is of a second conductivity type opposite to the first conductivity type; a second HVW region of the first conductivity type in the well region, wherein the second HVW region overlaps a portion of the buried well region; and a source region of the first conductivity type in a top region of the second HVW region.