| 发明名称 |
TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS |
| 摘要 |
Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed. |
| 申请公布号 |
US2016141212(A1) |
申请公布日期 |
2016.05.19 |
| 申请号 |
US201615008325 |
申请日期 |
2016.01.27 |
| 申请人 |
INTEL CORPORATION |
发明人 |
Govindaraju Sridhar;Prince Matthew J. |
| 分类号 |
H01L21/8234;H01L21/321;H01L21/3105;H01L27/088 |
主分类号 |
H01L21/8234 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material; depositing an electrically insulative material to fill regions between the individual lines; and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. |
| 地址 |
SANTA CLARA CA US |
