STATIC RANDOM ACCESS MEMORY FREE FROM WRITE DISTURB AND TESTING METHOD THEREOF

摘要

A static random access memory (SRAM) includes a memory cell array, a row decoder, a plurality of word-line drivers and an arbiter. The memory cell array includes a plurality of memory cell rows, wherein the memory cell rows are enabled by a plurality of word-lines, respectively. The row decoder is arranged to assert one of the memory cell rows according to a row address. The plurality of word-line drivers are each coupled to the row decoder and one of the memory cell rows. The arbiter is arranged to prevent multiple memory cells at a same word-line from being accessed at a same time.

主权项

1. A static random access memory (SRAM), comprising:
a memory cell array, comprising a plurality of memory cell rows, wherein the memory cell rows are enabled by a plurality of word-lines, respectively; a row decoder, arranged to assert one of the memory cell rows according to a row address; a plurality of word-line drivers, each coupled to the row decoder and one of the memory cell rows; and an arbiter, arranged to protect multiple memory cells at a same word-line from being accessed at a same time.