INSTRUCTION ORDERING FOR IN-PROGRESS OPERATIONS

摘要

Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

主权项

1. An apparatus comprising:
one or more modules configured to execute memory instructions that access data stored in physical memory based on virtual addresses translated to physical addresses based on mappings in a page table; and memory management circuitry coupled to the one or more modules, the memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses; wherein the memory management circuitry is configured to execute operations from the one or more modules, the executing including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in-progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in-progress operation depends on either or both of: (1) which of the one or more modules initiated the particular in-progress operation, or (2) whether or not the particular in-progress operation provides results to the first cache or second cache.